About this role
Senior RTL Design Engineer at Mythic-ai.com. Location: Austin or Palo Alto. Role: Designing RTL, Developing components, Collaborating teams Requirements: Experienced RTL design engineer with 8+ years in RTL, microarchitecture, and architecture development; strong Verilog/SystemVerilog and timing/EDA tools. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, EDA tools, Synthesis, Static timing analysis, Simulation, Linting Commitment: Full Time Workplace: Hybrid Languages: English