About this role
Senior NVM Circuit Designer at Mythic-ai.com. Location: Palo Alto or Austin or United States. Role: designing circuits, verifying IP, debugging silicon Requirements: Ph.D. or MS in EE or related,5–10+ years NVM memory design and tapeout experience,hands-on circuit simulation and silicon debugging,Python,Verilog-A,SystemVerilog RNM,SPICE and Cadence Virtuoso proficiency. Category: Engineering Seniority: Senior Level Tools: Verilog-A, System Verilog Real Number Modeling, Verilog, Python, SPICE, Cadence Virtuoso Commitment: Full Time Workplace: Hybrid Languages: English