About this role
Envision Employment Solutions is currently looking for a Senior Physical Design Engineer (Synthesis, SDC & STA) for one of our partners, an IT Services and IT Consulting company.
THE ROLE
Every constraint you write decides whether a chip closes timing or slips a tapeout. You'll own the front end of the physical design flow on advanced nodes, turning RTL into clean netlists with constraints that hold from synthesis all the way to signoff. When the timing report looks wrong, you're the one who knows whether it's the design, the constraint, or the tool.
WHAT YOU'LL DO
Own synthesis for complex blocks and full chip designs on 10nm and below nodesWrite, review, and debug SDC constraints, including partitioning and budgeting from top level to block levelDrive static timing analysis through to signoff, including SI and noise closureGenerate and implement functional and timing ECOsDevelop timing scripts for clock skew analysis, critical path analysis, and IO interface timingWork closely with RTL, DFT, and PnR teams to close PPA targetsSupport formal verification and low power implementation
WHAT WE'RE LOOKING FOR
10+ years of experience in physical design, with deep hands on work in synthesis, SDC and STAProven RTL to GDSII experience on 10nm or below nodes, with designs of 500k to 1M+ instancesPower user of Synopsys and/or Cadence synthesis and timing tools (Design Compiler, Genus, PrimeTime, Tempus)Strong STA/PTSI and signal integrity closure skillsGood knowledge of DFT scan insertion and its impact on timingProficiency in Tcl, Perl, Python and MakefileMultiple tapeouts with signoff closure
YOU'LL THRIVE HERE IF YOU
You treat a constraint file like code that deserves a proper reviewYou can explain a violating path to a designer in terms they can act onYou'd rather script a check once than eyeball a report a hundred timesYou stay calm when timing closure goes down to the wireYou enjoy being the person the whole flow depends on getting it right early