About this role
Envision Employment Solutions is currently looking for a Senior Physical Design Engineer (Floorplan & PnR) for one of our partners, an IT Services and IT Consulting company.
THE ROLE
A good floorplan makes every stage that follows easier, and a bad one haunts the project to tapeout. You'll own the implementation side of physical design, from partitioning and power planning through placement, CTS and routing, on some of the most advanced technology nodes out there.
WHAT YOU'LL DO
Own floorplanning, partitioning, pin assignment and power mesh design at block and full chip levelRun placement, CTS, routing and optimisation to close PPA targetsDrive clock tree planning and analysis, and scan reorderingClose physical verification: DRC, LVS, antenna, ERCResolve EM/IR issues and contribute to low power implementationWork closely with STA, DFT and RTL teams through to signoffComplete multiple design cycles with little supervision
WHAT WE'RE LOOKING FOR
10+ years of RTL to GDSII experience on 10nm or below nodes, with designs of 500k to 1M+ instancesPower user of PnR tools from Synopsys and/or Cadence (ICC2, Fusion Compiler, Innovus)Excellent floorplan, power plan, CTS, place, route and timing closure skillsStrong EM/IR, DRC, LVS and ERC analysis and fixingGood knowledge of synthesis and DFT scan insertionProficiency in Tcl, Perl, Python and MakefileTapeout experience; top level floorplanning is a plus
YOU'LL THRIVE HERE IF YOU
You can look at a floorplan and see the congestion before the tool doesYou enjoy the puzzle of balancing power, performance and areaYou work well on your own and still keep the wider team in the loopYou take pride in a clean DRC and LVS runYou want to work at the leading edge of process technology