About this role
Envision Employment Solutions is currently looking for a Senior DFT Engineer for one of our partners, an IT Services and IT Consulting company.
THE ROLE
A chip that can't be tested can't ship. You'll own design for test on large, complex SoCs, making sure every block can be scanned, patterned and diagnosed, and that test coverage stays high without costing the design its timing or area budget.
WHAT YOU'LL DO
Implement DFT in line with established test methodology on advanced process nodesPerform top and block level DFT insertion: scan compression, JTAG and IJTAG, MBIST and LBISTGenerate ATPG patterns, and run pattern validation and simulationWork closely with physical design to resolve DFT timing constraints and issuesVerify DFT logic and its interfaces with other IPs, and debug timing simulation issuesImprove test coverage and pattern efficiency, and handle hierarchical retargetingSupport silicon bring up, diagnosis and failure analysis
WHAT WE'RE LOOKING FOR
7+ years of hands on DFT experience on large, complex SoCsStrong knowledge of JTAG, ATPG, scan compression, IEEE 1500, MBIST and LBISTExperience with major EDA tools such as Synopsys DFT Compiler, TetraMAX, VCS, Siemens Tessent or Cadence ModusExperience in RTL simulation, synthesis, lint, CDC, RDC and STA is a plusScripting skills in Perl, Tcl and PythonStrong analytical and problem solving skills
YOU'LL THRIVE HERE IF YOU
You see test coverage as a quality metric, not a checkboxYou enjoy working across design, backend and silicon teamsYou like chasing a failing pattern until you find the real causeYou want to see your work pay off in the lab during bring upYou're always looking for a smarter way to compress patterns