About this role
Envision Employment Solutions is currently looking for a Lead STA Engineer for one of our partners, an IT Services and IT Consulting company.
THE ROLE
Timing signoff is the final word on whether a chip is ready, and you'll be the one giving it. As the lead STA specialist, you'll set the timing methodology, guide the team through closure, and make the call on what's truly clean. You'll be the reference point for anyone who needs to understand why a path is failing and what it will take to fix it.
WHAT YOU'LL DO
Lead full chip and block level STA and timing signoff on advanced nodes (10nm and below)Define timing methodology, signoff criteria, corners and modesOwn SI and noise analysis, OCV/AOCV/POCV strategy, and signoff closureDrive ECO generation and implementation for timing and functional fixesReview and guide constraint quality across RTL, synthesis and PnR teamsMentor and lead a team of timing engineersBuild and improve timing automation and reporting flows
WHAT WE'RE LOOKING FOR
10+ years of physical design experience, with a strong focus on STA and timing signoffProven experience leading timing closure on complex SoCs at 10nm or belowExpert level knowledge of PrimeTime and/or Tempus, including PTSIDeep understanding of SDC, multimode multicorner analysis and variation modellingStrong scripting in Tcl, Perl and PythonExperience leading or mentoring engineersMultiple successful tapeouts as timing owner
YOU'LL THRIVE HERE IF YOU
You're the one people call when nobody can explain a timing reportYou set the standard rather than follow someone else'sYou enjoy growing engineers as much as closing pathsYou can hold a firm line on signoff quality under schedule pressureYou think in corners, modes and margins without having to try