About this role
He is responsible to carry out all assigned tasks with focus on function, quality, test architecture, test coverage, schedule and delivery of verification in time.Together with other discipline's developers the Verification engineer is defining integration concepts, specifying the IC test requirements, defining related test architecture and verifying implemented functions. The is taking care about process implementation and scheduleIC (ASIC) Verification Engineer is responsible for developing functional models for Analog and/or Digital IPs, Developing Digital and Analog/Mixed signal Test-benches, Interaction between IPs at chip level (analog and digital), Developing test-benches, Functional verification, Technical support of co-workers and IP designers, Provide technical support to test engineersCollect, discuss and evaluate requirements related to IC test & validation concept(s) in cooperation with other discipline's developersActively support system and/or IC concept and architecture definition considering feasibility with semiconductor technologies and test strategyApply new validation concepts to the design verification.Define requirements of the IC validation together in cooperation with other discipline's developersSpecify IC validation characteristics and interfaces within component specification documentResponsible for the technical communication with the ASIC supplier during the whole ASIC developmentJudge and approve simulation/design results in consideration of defined system requirementsDecide on optimal IC verification concept based on simulation results and worst-case calculationsEvaluate technical and development risks for IC development together with ASIC PMPlan time schedule for dedicated ASIC project tasks, track validation progress, perform bench testsCreate and maintain development documentsApply configuration and change management, apply quality assurance managementFrom circuits specifications, ASIC verification engineer should specify verification strategies and testbench architectures (SystemVerilog, UVM, C-driven, others) to ensure optimum verification coveragesElaborate detailed verification plans corresponding to circuit specificationsDevelop verification environments and tests/sequences according to verification plansResponsible of the definition of the verification strategies, of their implementation and of the verification qualityImprove the verification flow Master of Science in Electrical Engineering/Microelectronics/ VLSI design or similar qualification.Bachelor of science with advanced course in VLSI Design. Integrated circuits digital/ analog (e.g. high voltage analog CMOS and BCD)10+ years experience in IC design and verification / validationAutomotive product developmentIC design/synthesis tools, good understanding of the physical design flow a plus (e.g. Cadence, Synopsys)Office tools (e.g. MS office, Visio)Worked on IPs (e.g. SPI, I2C, HDMI, RSDS, OpenLdi, PSI5, Ethernet, CAN…)VDHL, VerilogUVM test methodologySystem Verilog, SystemC (optional)Working in international development networkReady to take your career to the next level? The future of mobility isn’t just anyone’s job. Make it yours! Join AUMOVIO. Own What’s Next.