About this role
Principal Engineer Chip Architect (f/m/div) at Infineon. Location: Villach, Carinthia, Austria. Role: defining architecture, conducting feasibility, providing guidance Requirements: University degree in EE/Microelectronics/Physics, 6+ years in integrated analog/mixed-signal design, Cadence Virtuoso and AMS Designer knowledge, SystemVerilog/RTL advantage, experience in power applications a plus, fluent English. Category: Research and Development (R&D) Seniority: Senior Level Tools: Cadence Virtuoso, AMS Designer, SystemVerilog, RTL Commitment: Full Time Workplace: Onsite Languages: English