About this role
Principal DFT Engineer at Fortell. Location: San Jose, California, United States. Role: design DFT, implement testing, debug silicon Requirements: Experience designing and implementing DFT, ATPG, JTAG, MBIST; Cadence Modus/Genus proficiency; TCL scripting; Bay Area resident. Category: Engineering Seniority: Senior Level Tools: Cadence Modus, Cadence Genus, ATPG, MBIST, JTAG, Tensor, TCL, Boundary Scan, Scan Chains Commitment: Full Time Workplace: Hybrid Languages: English