About this role
Sr. Engineer, Layout Design at SiTime. Location: Shinagawa, Tokyo, Japan. Role: leading chip-planning, performing layout, verifying layouts Requirements: BA/BS or equivalent experience, 10+ years layout design experience for analog and full-custom digital blocks; proficiency with Cadence Virtuoso, debug DRC/LVS/ERC with Cadence PVS or Mentor Calibre; experience with TSMC 180nm/65nm/22nm. Category: Engineering Seniority: Senior Level Tools: Cadence Virtuoso, Cadence PVS, Mentor Calibre Commitment: Full Time Workplace: Onsite Languages: English