About this role
Sr. Engineer, Analog Mixed-Signal Design at SiTime. Location: Rijswijk, Zuid-Holland, Netherlands. Role: designing circuits, verifying simulations, bringing up Requirements: M.S. in EE + 4 years or Ph.D. in EE + 2 years; expertise in CMOS analog/mixed-signal design, PLLs, ADCs, low-noise circuits; MATLAB, VerilogA, and Cadence experience; strong communication and teamwork. Category: Engineering Seniority: Senior Level Tools: MATLAB, VerilogA, Cadence Commitment: Full Time Workplace: Onsite Languages: English