About this role
Pre-si Verification Engineer at Intel. Location: Bangalore, Karnataka, India. Role: developing testbench, executing verification, debugging failures Requirements: 8–15 years pre-silicon SoC/subsystem/IP verification experience; SystemVerilog/UVM testbench development, simulation/emulation, debug, coverage-driven verification; BE/BTech (ECE/CS) or MTech; BLS not applicable. Category: Engineering Seniority: Senior Level Tools: System Verilog, UVM Commitment: Full Time Workplace: Hybrid Languages: English