About this role
Design Verification Architect at Intel. Location: Folsom or Santa Clara. Role: defining strategy, architecting testbenches, verifying integration Requirements: Bachelor's in Electronics/Computer Engineering with 6+ years or Master's with 4+ years; strong experience in frontend validation, simulation/testbench development, functional/code coverage closure; proficiency in C/C++, Python, and SystemVerilog; familiarity with IP validation and security validation. Category: Engineering Seniority: Mid Level Tools: C, C++, Python, System Verilog, UVM, OVM, formal verification tools Commitment: Full Time Workplace: Hybrid Languages: English