About this role
Senior Design Verification Engineer at Intel. Location: Bangalore, Karnataka, India. Role: developing plans, creating testbenches, debugging issues Requirements: 4+ years (B.S.) or 3+ years (M.S.) experience in IP-level design verification; proficiency in SystemVerilog, hardware simulation, OVM/UVM, knowledge of AMBA/PCIe/CXL protocols; strong communication and critical thinking; Bachelor's or Master's in EE/CS or related. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, OVM, UVM, AMBA AXI/ACE/CHI, PCIe, CXL Commitment: Full Time Workplace: Onsite Languages: English