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Scientist, Electrical Engineer 1 (Yorba Linda, CA, US, 92887) @ L3Harris Technologies, Inc.

Yorba Linda, California, USOnsiteFull-time
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<p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Job Title: Scientist, Electrical Engineer - Hardware &amp; RF</span></strong></span></em></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Job Code: 34982</span></strong></span></em></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Job Location:</span></strong><strong> Yorba Linda, CA</strong></span></em></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><em><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Work Schedule: 4/10 Employees work 10 hour days, 4 days a week</strong></span></em></p> <p style="line-height:105%;margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Job Description:</span></strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="color:black">L3Harris is looking for candidates for the Scientist in Hardware and RF Electrical Engineering in our Navigation Solutions (NS) business in Yorba Linda, CA (IEC). The candidate will be responsible for and provide senior hands-on expert level in hardware and RF Electrical engineering on multiple programs. The candidate must have deep Engineering and broad Engineering technical expertise, industry recognition in defense and commercial applications, and experience in military GPS and Position Navigation and Timing (PNT) technology or other RF hardware designs and hands-on. Our Navigation Solutions products provide advanced military GPS and Position, Navigation, Timing (PNT) capabilities in military embedded real-time systems that can be used in weapons, ground, airborne, maritime, and space environments</span><em><span style="color:black">.</span></em></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Essential Functions:</strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black">Must provide overall hands-on technical expertise in Hardware and RF Electrical Engineering for NS programs.</span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black">Expert hands-on knowledge of Electrical Engineering low frequency and high frequency (RF) analog and CCA design.</span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black;background-color:white">Requires comprehensive level knowledge of Electrical Engineering low frequency and high frequency (RF) Analog and Digital circuit design.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Experience with RF systems, ideally GPS receivers</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Able to contribute to providing innovative Electrical Engineering solutions consistent with business development plans.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to develop circuit designs, requirements, design descriptions, verification plans/procedures, customer CDRLs to meet program schedules.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to support cross functional teams for cross functional conflict resolution, Root Cause Analysis, blank page architecture developments and design</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to contribute to algorithm development, analysis, implementation, system architecture, verification, and Test with emphasis on military GPS electronics. </span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to contribute to execution of design, build, integration and test activities, problem resolution and verifying that the deliverable products meet all program and customer requirements.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to provide project management reports as required, support senior level and customer reviews as necessary.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to provide inputs and reviews of the engineering technical baseline as part of proposal efforts.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to interface with the program’s leadership and other teams (SW, Systems, ME, and Test) on a frequent basis, conduct or participate in customer and/or program technical review presentations, and provide progress status updates on work products.</span></li> <li style="margin:0.0in 0.0in 8.0pt 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif;color:black">Ability to participate or lead in the product development process including design reviews.</span></li> </ul> <p style="line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif;margin:0.0in 0.0in 8.0pt 5.0px"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Qualifications:</span></strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black;background-color:white">Bachelor’s degree in electrical engineering and a minimum of 12 years of prior relevant experience. Graduate Degree and a minimum of 10 years of prior related experience. In lieu of a degree, minimum of 16 years of prior related experience.</span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="color:#242424">Minimum of 7 years’ experience in ability to capture schematics design and PCBA Layout using modern EE CAD such as Altium or Mentor Graphics</span><span style="color:black">. </span></span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#242424">5 years’ experience with project management and product design team leadership guided by individual annual goals and objectives with minimal oversight or direction; working in a team environment as an individual contributor. </span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#242424">8 years’ strong experience with receiver, Antenna, or Radio design (i.e. RF).</span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#242424">4 years’ experience with embedded Hardware design.</span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:#242424">4 years’ experience demonstrating strong verbal and written skills</span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;font-family:verdana, geneva, sans-serif;color:black">7 Years experience with design tools such as MATLAB/Simulink, P-Spice, Agilent ADS (or AWR), Schematics Capturing/PCBA Layout tools such as Altium, Mentor Graphics, and Ansys HFSS</span></li> <li style="background-color:white;margin:0.0in 0.0in 0.0in 5.0px;font-size:14.0pt;font-family:verdana, geneva, sans-serif"> <p style="margin:0.0in;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif">Active Secret security clearance.</span></p> </li> </ul> <p style="margin:0.0in 0.0in 0.0in 39.75pt;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in 0.0in 0.0in 39.75pt;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in 0.0in 0.0in 39.75pt;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong><span style="color:black">Preferred Additional Skills:</span></strong></span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"> </p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Recognized as an Analog RF Electrical and Radio Receivers expert in industry.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Experience and understanding in detailed RF receiver designs in military GPS, MGNSS, and other PNT technology.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Strong familiarity with modern GPS Module design and topology. </span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Advanced with High-speed Analog design methodologies. </span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Experience with HAM radio is a plus.</span></li> <li style="margin:0.0in 0.0in 0.0in 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Advanced in MS Office, design tools such as Simulink/MATLAB, P-Spice, Altium (Schematics Capturing &amp; PCBA Layout), Agilent ADS (or AWR), and Ansys HFSS.</span></li> <li style="margin:0.0in 0.0in 8.0pt 5.0px;line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:verdana, geneva, sans-serif">Proficient with DO-254 design.</span></li> </ul> <p style="line-height:107%;font-size:14.0pt;font-family:verdana, geneva, sans-serif;margin:0.0in 0.0in 8.0pt 5.0px"> </p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">In compliance with pay transparency requirements, the salary range for this role in California, </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Massachusetts, New Jersey, Washington, and the Greater D.C, Denver, or NYC areas is $150,000 -</span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">$278,000. The salary range for this role in Colorado state, Hawaii, Illinois, Maryland, Minnesota, New </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">York state, Cleveland Ohio, and Vermont is $130,500 - $242,500. This is not a guarantee of </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">compensation or salary, as final offer amount may vary based on factors including but not limited to </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">experience and geographic location. L3Harris also offers a variety of benefits, including health and </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">paid time off, and company-paid holidays. The specific programs and options available to an employee </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">may vary depending on date of hire, schedule type, and the applicability of collective bargaining </span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">agreements.</span></p> <p style="margin:0.0in;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">#LI-KA1</span></p>

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