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Hardware Design Verification Engineer (SystemVerilog) @ Actalent

Redmond, Washington, USOnsiteContract
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About this role

Exciting opportunity for a Hardware Design Verification Engineer and play a key role in validating advanced networking hardware. Leverage your expertise in SystemVerilog and UVM to ensure robust, functional designs. Collaborate with cross-functional teams and drive innovation in a fully remote, 12-month contract. Shape the future of hardware verification with us!. Category: Manufacturing, Mechanical, & Electrical

Skills

systemveriloguvmhardware design verificationrtl design and verificationtest plan executiondebuggingscenario validationhardware functionality validationsystem-level validationprototype testingnetworking hardware

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