About this role
Design Engineer at Astera Labs. Location: Israel. Role: Design ownership, Quality assurance, Design optimization Requirements: Senior VLSI Design Engineer with 3+ years in logic design, Verilog/SystemVerilog, and cross-team collaboration. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, EDA tools, Python Commitment: Full Time Workplace: Onsite Languages: English