About this role
Technical Lead Physical Design Engineer at Astera Labs. Location: Toronto, Ontario, Canada. Role: driving timing, developing constraints, managing runs Requirements: Bachelor's in EE/CS required (Master's preferred), ≥5 years STA/timing sign-off for complex SoCs, expertise in STA, SDC, synthesis/P&R flows, Cadence/Synopsys toolchains, and scripting (Tcl, Python, Perl). Category: Engineering Seniority: Senior Level Tools: Cadence, Synopsys, Tcl, Python, Perl, SystemVerilog, Verilog, ETM Commitment: Full Time Workplace: Onsite Languages: English