About this role
Senior Engineer, Analog Mixed Signal Layout at Astera Labs. Location: Ho Chi Minh City, Ho Chi Minh City, Vietnam. Role: designing layout, managing manufacturing, developing tests Requirements: Bachelor's in electrical engineering, 4+ years layout experience for high-speed analog ICs in finFET, proficiency with layout extraction and parasitic analysis, EMIR/antenna-aware DRC practices, and experience writing SKILL and TCL scripts. Category: Engineering Seniority: Mid Level Tools: SKILL, TCL, COSMOS, DRC, LVS Commitment: Full Time Workplace: Onsite Languages: English