About this role
Principle Design Verification Engineer SerDes/PHY at Astera Labs. Location: San Jose, California, United States. Role: architecting verification, developing testbenches, mentoring engineers Requirements: Bachelor's in EE/CE required, 8+ years verification experience on high-speed SerDes/PHY or mixed-signal IP, expert SystemVerilog/UVM, RNM and analog/mixed-signal co-simulation, protocol knowledge (PCIe/UALink/UCIe/Ethernet/CXL); mentoring and leadership experience. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Real Number Modeling (RNM), Palladium, Veloce, ZeBu, Python, Perl, PCIe, UALink, UCIe, Ethernet, CXL, COSMOS Commitment: Full Time Workplace: Onsite Languages: English