About this role
Sr. Analog Design Engineer at Credo. Location: San Jose, California, United States. Role: designing blocks, running simulations, testing designs Requirements: M.S. or Ph.D. in Electrical Engineering, 5+ years IC development with advanced CMOS (FinFET) experience; strong analog/mixed-signal circuit knowledge; proficiency with Cadence Virtuoso, Synopsys Custom Compiler, MATLAB, and Verilog. Category: Engineering Seniority: Senior Level Tools: Cadence Virtuoso, Synopsys Custom Compiler, MATLAB, Verilog Commitment: Full Time Workplace: Onsite Languages: Chinese, English