About this role
Sr. Staff Digital Design Engineer at Credo. Location: Pittsburgh, Pennsylvania, United States. Role: leading evaluations, defining roadmaps, developing RTL Requirements: 10+ years experience with digital ASIC/RTL design, Verilog/SystemVerilog, networking protocols (Ethernet, PCIe, CXL, UCIe, UALink), Unix/Linux scripting, Cadence/Mentor/Synopsys tool experience, strong technical leadership and debugging skills. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, Perl, Tcl, Python, Shell, Cadence, Mentor, Synopsys, UVM Commitment: Full Time Workplace: Onsite Languages: English