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Senior Specialist, Systems Engineer - ELINT (Greenville, TX, US, 75402) @ L3Harris Technologies, Inc.

Greenville, TX, US, 75402OnsiteFull-time
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<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Title:</strong> Senior Specialist, Systems Engineer - ELINT</span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Code:</strong> 39540</span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Location:</strong> Greenville, TX</span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Schedule:</strong> 9/80 - Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off</span></p> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Job Description:</strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">L3Harris is seeking a Systems Engineering Specialist who will be involved in activities directly related to the design, and development of complex, specialized SIGINT hardware/software systems to process and manipulate ISR data from multiple data sources.</span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong> </strong></span></p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Essential Functions: </strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Works closely with the customer to comprehensively design and implement new system functionality.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Writes requirements, supports development, performs integration testing of new or modified products in a Systems Integration Laboratory and on airborne and ground-based platforms.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Verifies and validates new baseline functionality while ensuring legacy functionality continues to work as intended.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Interface with other Systems Engineers, Agile Development Engineering, Flight Line Test, Product Development, and Project Engineering to understand new baseline functionality.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work closely with L3Harris Internal Research and Development (IR&amp;D) developing proprietary ELINT technology and capabilities.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Follow existing standards to document system testing status and anomalies with system hardware and software and verifies subsequent anomaly fixes.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Interfaces with the customer to ensure their satisfaction with system performance.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work with management to develop and adhere to schedules and budgets required to accomplish assigned work.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Provide regular status updates for ongoing work efforts to management and the customer.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Work effectively in a fast-paced, dynamic environment with time-critical requirements.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Effective cross-functional communication skills supporting program execution from development through integration and delivery.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Analysis of customer requirements, including system and sub-system trade studies, and detailed hardware and software specifications for systems, subsystems, and key components.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Development of test planning/procedures of various test equipment including anechoic chambers, spectrum analyzers, and network analyzers.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Entire Program/Engineering Life Cycle Phases and Activities.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">IRAD and Technical Baseline development.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Requirements Management.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Strong problem‑solving abilities with thorough documentation, verification, and validation practices</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Proficiency in digital signal processing (DSP) with strong MATLAB skills for algorithm development, modeling, simulation, and data analysis</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Solid understanding of DSP fundamentals including filtering, spectral analysis, FFTs, modulation, sampling theory, and noise reduction</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Ability to support algorithm implementation in C, C++, or Python</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Active Secret or recent TS/SCI Clearance with the ability to maintain.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Working contract proposals.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Travel up to 10%.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Other duties as assigned by Supervisor.</span></li> </ul> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Qualifications:</strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Bachelor’s Degree and minimum 6 years of prior relevant engineering experience.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Graduate Degree and a minimum of 4 years of prior related engineering experience.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">In lieu of a degree, a minimum of 10 years of prior related engineering experience.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated understanding of RF and microwave fundamentals, including antennas, receivers, spectral behavior, and front-end design.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated experience with signals analysis techniques and tools, including pulse analysis, modulation assessment, and emitter characterization.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Demonstrated knowledge of radar fundamentals such as pulse radar, CW/FMCW, LPI principles, scan patterns, and threat system behavior.</span></li> </ul> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><strong>Preferred Additional Skills:</strong></span></p> <ul> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Active TS/SCI Clearance</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with integration and troubleshooting of complex RF or electronic warfare receiver systems.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with JIRA, Confluence, and DOORS for requirements and workflow management.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience in MATLAB and Python for algorithm development, modeling, automation, data analysis, and visualization.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience working with large IQ/sample data sets and developing automated processing workflows.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience with advanced DSP algorithm development and implementation.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Familiarity with system‑level SEI, LPI/LPE techniques, or advanced emitter analysis methodologies.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Experience in software integration and system-level test.</span></li> <li style="font-family:verdana, geneva, sans-serif;font-size:14.0pt"><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">Proficiency with standard office and documentation tools.</span></li> </ul> <p> </p> <p> </p> <p> </p> <p> </p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt">#LI-AM2</span></p>

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