About this role
Lead Design Engineer at Cadence. Location: Bangalore, Karnataka, India. Role: leading prototyping, designing hardware, debugging systems Requirements: Experience in post-silicon PHY and subsystem validation for high-speed SERDES, lab debug skills, 2-3 years managing engineers, BE/BTech or ME/MTech degree, Verilog/Python/C/C++ familiarity. Category: Engineering Seniority: Senior Level Tools: NCSIM, Palladium, Verilog, python, C, C++, Oscilloscope, Bit Error Rate Tester, Protocol Exerciser, Analyzer Commitment: Full Time Workplace: Onsite Languages: English