About this role
Principal DFT Engineer at Cadence. Location: Bangalore, Karnataka, India. Role: inserting scan, debugging failures, verifying tests Requirements: 7+ years SoC/ASIC digital design experience with emphasis on design-for-test (scan insertion, compression, LBIST, MBIST), ATPG, failure debug, and collaboration across cross-functional teams. Category: Engineering Seniority: Senior Level Tools: Cadence Commitment: Full Time Workplace: Onsite Languages: English