About this role
Principal Analog Design Engineer - Power management at TYLsemi, Inc.. Location: Bangalore or India. Role: designing regulators, modeling subsystems, leading collaboration Requirements: 12+ years analog/mixed-signal IC design experience in high-current power management; expertise in regulator topologies, magnetics integration, packaging co-design; proficiency with Cadence Virtuoso, Spectre, Clarity/EMX, MATLAB/Simulink. Category: Research and Development (R&D) Seniority: Senior Level Tools: Cadence Virtuoso, Spectre, Clarity/EMX, MATLAB/Simulink Commitment: Full Time Workplace: Hybrid Languages: English