About this role
Senior Engineer – LEC / CLP (Logical Equivalence & Low Power Convergence) at TYLsemi, Inc.. Location: Bangalore or India. Role: performing equivalence, validating low-power, debugging failures Requirements: Bachelor's or Master's in Electrical/Electronics engineering, 5+ years in formal verification/LEC/low-power verification, experience with Cadence Conformal or Synopsys Formality, UPF/CPF, synthesis and equivalence debugging, scripting in TCL/Python/Perl. Category: Research and Development (R&D) Seniority: Senior Level Tools: Cadence Conformal, Synopsys Formality, UPF, CPF, TCL, Python, Perl Commitment: Full Time Workplace: Hybrid Languages: English