About this role
Principal FPGA Design Engineer at SiTime Corporation. Location: Santa Clara, California, United States. Role: architect FPGA, lead initiatives, define requirements Requirements: Seasoned FPGA architect with 10+ years of hands-on FPGA design and leadership experience. Category: Engineering Seniority: Senior Level Tools: Verilog, VHDL, ModelSim, Vivado, Python, TCL, PCIe, DDR, SERDES Commitment: Full Time Workplace: Onsite Languages: English