About this role
ASIC Design Team Lead at Arcfield. Location: Home, New York, United States. Role: lead team, develop RTL, verify design Requirements: Bachelor/Master/PhD in Hardware/EE with extensive experience; Secret clearance; FPGA/HDL design expertise; leadership experience. Category: Engineering Seniority: Senior Level Tools: VHDL, Verilog, ModelSim, QuestaSim, Cadence Virtuoso, Xilinx FPGA, HDL, Synopsys, Genus Certifications: security clearance: secret Commitment: Full Time Workplace: Remote Languages: English