About this role
Lead MTS Verification Engineering at Rambus. Location: Bangalore, Karnataka, India. Role: developing testbench, planning coverage, debugging RTL Requirements: Bachelors in EE/CS, 5+ years HDL design-verification experience, SystemVerilog/UVM and Verilog fluency, PCI-Express controller familiarity required; Python and Tcl scripting preferred. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Verilog, Python, Tcl Commitment: Full Time Workplace: Hybrid Languages: English