About this role
Digital Design Verification, Principal Engineer-17853 at Synopsys. Location: Austin, Texas, United States. Role: applying AI, implementing flows, mentoring engineers Requirements: 12+ years IP/SoC verification experience, proficiency with Synopsys verification tools, agentic AI exposure, scripting in SystemVerilog/UVM/Tcl/Python, and BS/MS in electrical/electronics/computer engineering. Category: Engineering Seniority: Senior Level Tools: VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), VIPs, Cursor, Microsoft VS Code co-pilot, SystemVerilog, UVM, Tcl, Python Commitment: Full Time Workplace: Onsite Languages: English