About this role
Senior Application Engineer - Design Verification at proteanTecs. Location: Santa Clara or Israel or United States or India or Korea or Taiwan. Role: enabling customers, integrating IP, debugging issues Requirements: Bachelor's/Master's in EE/CpE or related with 3+ years experience; advanced DV flow development, SystemVerilog/UVM, testbench architecture, RTL/gate-level debugging, SoC architecture, and strong customer-facing/problem-solving skills. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, UVM, EDA tools Commitment: Full Time Workplace: Hybrid Languages: English