About this role
Principal Physical Design Engineer (Full Chip Expert) at Aion Silicon. Location: Africa or Asia or Spain or London or Bristol. Role: leading implementation, mentoring engineers, defining strategy Requirements: 10+ years physical design experience delivering full-chip SoC/ASIC tape-outs on advanced nodes (7nm/5nm), expertise across floorplanning, CTS, power/package integration, EDA tool flows; strong leadership and stakeholder skills. Category: Engineering Seniority: Senior Level Tools: Synopsys ICC2, Synopsys Fusion Compiler, Synopsys PrimeTime, Synopsys StarRC, Synopsys ICV, Cadence Innovus, Cadence Tempus, Cadence Voltus, Cadence Genus, Mentor Calibre Commitment: Full Time Workplace: Hybrid Languages: English