About this role
Principal Physical Design Engineer (Full Chip Expert) at Aion Silicon. Location: Africa or Asia or Spain or London or Bristol. Role: leading implementation, mentoring engineers, driving tape-outs Requirements: 10+ years physical design experience for full-chip SoC/ASIC delivery on advanced nodes (7nm/5nm+), expertise across floorplanning, placement/routing, CTS, power planning, DRC/LVS sign-off, EDA tool flows, and leadership/mentoring skills. Category: Engineering Seniority: Senior Level Tools: Synopsys ICC2, Synopsys Fusion Compiler, Synopsys PrimeTime, Synopsys StarRC, Synopsys ICV, Cadence Innovus, Cadence Tempus, Cadence Voltus, Cadence Genus, Mentor Calibre Commitment: Full Time Workplace: Hybrid Languages: English