About this role
Digital Design Engineer at Silvaco. Location: Cairo, Egypt. Role: developing rtl, conducting verification, performing synthesis Requirements: Bachelor's in Electronics Engineering,0-3 years VLSI digital design/verification experience, strong Verilog RTL knowledge, CDC/RDC techniques, ASIC/FPGA flows, static timing analysis and synthesis experience. Category: Engineering Seniority: No Prior Experience Required Tools: Verilog, System Verilog, UVM, FPGA, Unix, Linux Commitment: Full Time Workplace: Onsite Languages: English