About this role
FPGA Engineer at Fortaegis. Location: Amsterdam, North Holland, Netherlands. Role: designing logic, implementing designs, testing designs Requirements: 5+ years FPGA design experience, hands-on with Xilinx FPGAs, Vivado, Vitis; strong digital design, timing and high-speed interfaces knowledge; VHDL/Verilog/SystemVerilog experience; lab validation skills. Category: Engineering Seniority: Senior Level Tools: Xilinx FPGAs, Vivado, Vitis, VHDL, Verilog, SystemVerilog Commitment: Full Time Workplace: Onsite Languages: English