About this role
Hardware Security Engineer at Fortaegis. Location: Amsterdam, North Holland, Netherlands. Role: designing modules, implementing countermeasures, analyzing leakage Requirements: Proven RTL (SystemVerilog/VHDL) experience for ASIC/FPGA, deep knowledge of AES/ECC/SHA, hands-on side-channel countermeasure implementation, and familiarity with SCA tools. Category: Engineering Seniority: Mid Level Tools: RTL, SystemVerilog, VHDL, Verilog, AES, ECC, SHA, ChipWhisperer, DPA, CPA, SCA Commitment: Full Time Workplace: Onsite Languages: English