About this role
Design Verification Engineer at Fortaegis. Location: Amsterdam, North Holland, Netherlands. Role: verifying designs, developing environments, debugging issues Requirements: 5+ years RTL functional verification for FPGA/ASIC, advanced SystemVerilog and UVM knowledge, experience with Siemens/Cadence/Synopsys EDA tools, strong analytical and communication skills. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Siemens, Cadence, Synopsys Commitment: Full Time Workplace: Onsite Languages: English