About this role
Senior/Principal Full-Chip Physical Verification Engineer at Celero Communications, Inc.. Location: San Jose or Irvine. Role: leading verification, owning execution, analyzing results Requirements: 7+ years full-chip physical verification experience, BS in Electrical Engineering (MS preferred), hands-on with ICV or Calibre, DRC/ERC analysis, tapeout experience, floorplanning expertise; Tcl/Python/shell scripting preferred. Category: Engineering Seniority: Senior Level Tools: ICV, Calibre, Tcl, Python, shell Commitment: Full Time Workplace: Onsite Languages: English