About this role
ASIC Design Engineer at Celero Communications, Inc.. Location: Ottawa or Cordoba. Role: design circuits, verify designs, optimize performance Requirements: 4+ years in digital design/verification; degree in Electrical or Computer Engineering; proficiency in Verilog/SystemVerilog; knowledge of ASIC flow and low-power techniques; UVM/formal verification; DSP/communication knowledge preferred. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, HDL, UVM, Formal Verification, Synthesis, Timing Analysis, EDA Tools Commitment: Full Time Workplace: Onsite Languages: English