About this role
ASIC Digital Design, Staff Engineer -18138 at Synopsys. Location: Boxborough, Massachusetts, United States. Role: designing RTL, optimizing design, developing automation Requirements: 5+ years ASIC digital design experience with RTL ownership; proficiency in Verilog and Perl; deep knowledge of synthesis, timing analysis, power optimization; BS/MS in EE/CE. Category: Engineering Seniority: Senior Level Tools: Verilog, Perl Commitment: Full Time Workplace: Onsite Languages: English