About this role
SOC Verification, Sr Engineer at Synopsys. Location: Noida, Uttar Pradesh, India. Role: building verification, developing testbenches, debugging simulations Requirements: 2+ years verification experience with SystemVerilog/UVM; experience with VCS, waveform debugging, integrating VIPs, scripting (shell/Makefile/Perl); bachelor's or master's in electronics engineering or related field. Category: Engineering Seniority: Entry Level Tools: SystemVerilog, UVM, VCS, Synopsys VIP, AXI, USB, PCIe, MIPI, shell, Makefile, Perl Commitment: Full Time Workplace: Onsite Languages: English