About this role
Lead SoC Design Engineer at Anodize. Location: Los Altos, California, United States. Role: authoring microarchitecture, driving PPA, owning RTL Requirements: 10+ years developing complex ASICs; Bachelor's in EE/CE (or equivalent); deep knowledge of AMBA protocols, Verilog/SystemVerilog/SVA, SDC timing constraints, multi-power-domain design and UPF; experience with ASIC CAD flows. Category: Engineering Seniority: Senior Level Tools: AMBA AXI, AXI-S, APB, Verilog, SystemVerilog, SystemVerilog Assertions (SVA), SDC, STA, Lint, CDC, RDC, LEC, UPF, UCIe, DDR, Arm Commitment: Full Time Workplace: Onsite Languages: English