About this role
AI Silicon, Digital Design Engineer at Unconventional, Inc.. Location: Palo Alto, California, United States. Role: leading integration, implementing RTL, mentoring engineers Requirements: B.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills. Category: Engineering Seniority: Senior Level Tools: Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) Commitment: Full Time Workplace: Onsite Languages: English