About this role
Junior AI Silicon, Digital Design Engineer at Unconventional, Inc.. Location: Palo Alto, California, United States. Role: designing soc, implementing rtl, performing synthesis Requirements: B.S./M.S. in EE/Computer Engineering, 4+ years ASIC/SoC digital design experience, Verilog/SystemVerilog RTL development, synthesis/timing and CDC/Lint/LEC familiarity, EDA tool experience, strong communication. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, UVM, Logic Equivalence Checking (LEC), EDA tools, logic analyzer, oscilloscope Commitment: Full Time Workplace: Onsite Languages: English