About this role
Digital Design Intern at Silvaco. Location: Cairo, Cairo Governorate, Egypt. Role: designing RTL, simulating designs, supporting projects Requirements: Bachelor's in Electronics Engineering required; strong Verilog RTL design/simulation knowledge; familiarity with CDC/RDC, ASIC/FPGA flows, STA/SDC; System Verilog/UVM, Unix/Linux and shell scripting desirable. Category: Engineering Seniority: Entry Level Tools: Verilog, System Verilog, UVM, Unix/Linux, shell scripting Commitment: Full Time, Internship Workplace: Onsite Languages: English