Senior Specialist, Radio Frequency Design Engineer (Plano, TX, US, 75074) @ L3Harris Technologies, Inc.

<p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt;color:black"><em><strong>Job Title: Senior Specialist, Radio Frequency Design Engineer </strong></em></span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt;color:black"><em><strong>Job Code: 39485</strong></em></span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt;color:black"><em><strong>Job Location: Plano, Texas</strong></em></span><br><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt;color:black"><em><strong>Job Schedule: 9/80: Employees work 9 out of every 14 days – totaling 80 hours worked, and have every other Friday off</strong><br> </em></span></p> <div class="WordSection1"> <h1 style="margin:0.0in 0.0in 0.0in 5.2pt;font-size:14.0pt;font-family:Verdana, sans-serif">Job Description:</h1> <p style="margin:0.45pt 0.0in 1.0E-4pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><strong> </strong></p> <p style="margin:0.0in 5.15pt 1.0E-4pt 5.2pt;text-indent:0.0in;line-height:100%;font-size:14.0pt;font-family:Verdana, sans-serif">As RF Circuit Design Engineer, you will be responsible for participating in the design, simulation, development, and testing of RF circuits, antenna systems or systems for use in Radar systems or other tactical military applications.</p> <p style="margin:12.25pt 5.15pt 1.0E-4pt 5.2pt;text-indent:0.0in;line-height:100%;font-size:14.0pt;font-family:Verdana, sans-serif">L3Harris’ Agile Development Group specializes in developing disruptive, next-generation technologies for advanced Unmanned Air Systems (UAS / UAV), advanced radar systems, next-generation weapon systems, and other RF sensor technologies using small company agility and big company experience.</p> <p style="margin:0.6pt 0.0in 1.0E-4pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"> </p> <h1 style="margin:0.0in 0.0in 0.0in 5.2pt;font-size:14.0pt;font-family:Verdana, sans-serif">Essential Functions:</h1> <p style="margin:12.2pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Take responsibility for electrical design tasks including requirements analysis, specification generation, interface definition, component selection, circuit simulation, schematic capture, and board layout.</p> <p style="margin:0.2pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Provide technical responsibility for schedule, cost, and performance at the board or subsystem level.</p> <p style="margin:0.15pt 28.75pt 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Perform RF &amp; Microwave (VHF through Ka-Band) design synthesis at the board or subsystem level.</p> <p style="line-height:100%;margin:0.15pt 0.0in 0.0in 29.2pt;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Perform simulation, breadboarding, testing &amp; troubleshooting of RF circuits, functions and subsystems.</p> <p style="margin:0.1pt 0.0in 1.0E-4pt 14.95pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;font-family:'Times New Roman', serif"> </span>Develop test plans and procedures for RF subsystems.</p> <p style="margin:0.25pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Participate in peer reviews, preliminary design reviews, critical design reviews and other required design reviews.</p> <p style="margin:0.1pt 0.0in 1.0E-4pt 14.95pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;font-family:'Times New Roman', serif"> </span>Participate in interdisciplinary design teams and reviews.</p> <p style="margin:0.25pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Learn and follow company processes for product development, configuration management, purchasing, etc.</p> <p style="margin:0.15pt 131.85pt 1.0E-4pt 14.95pt;text-indent:0.0in;line-height:100%;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Physical Requirements: ability to lift up to 10 pounds. <span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-family:'Times New Roman', serif"> </span>Up to 10% travel may be required.</p> </div> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt;color:black"><strong><span style="font-size:14.0pt;line-height:100%;font-family:Verdana, sans-serif"> </span></strong></span></p> <h1 style="margin:3.65pt 0.0in 0.0in 5.2pt;font-size:14.0pt;font-family:Verdana, sans-serif">Qualifications:</h1> <p style="margin:12.25pt 0.0in 1.0E-4pt 14.95pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;font-family:'Times New Roman', serif"> </span>Active US secret security clearance.</p> <p style="margin:0.25pt 7.9pt 1.0E-4pt 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Bachelor’s Degree in Electrical Engineering and minimum 7-10 years of prior relevant experience. </p> <ul> <li style="line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"> Graduate Degree in Electrical Engineering and a minimum of 4 years of prior related experience.</li> <li style="line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"> In lieu of a degree, minimum of 10 years of prior related experience.</li> </ul> <p style="margin:0.3pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span> 4+ years of experience with RF and 3D EM Simulation and Modeling, Schematic Capture, Board Layout CAD tools</p> <p style="margin:0.15pt 28.75pt 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>4 years of experience with practical RF system considerations such as path loss calculation, cascade noise figure, intercept point and power and corresponding tests for each.</p> <p style="margin:0.2pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ2DQAxFv0lLARmA6grfRGlhgzSww90SSc1AgJTqFkCR3PPTBIkiCmDpd+/bsv1BEiRhZnmMsfXeDyKyiMjivR9ijK2Z5SsHkkgpVc65FwD+knPulVKqSAJmlv+DtyYzyy9FUdz7vr9hp+Z5vpZl+YaqjnvdV333k4Wk7E0AABFhdgTcVqaq01FYVaesruvnUUPTNI/TZz3/uG00Qgidqo5rNFR1DCF022h8AKIHnGgu23DPAAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>4 years of experience with basic RF test equipment including Network Analyzers, Spectrum Analyzers, and Signal Generators.</p> <p style="margin:0.1pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>4 years of experience in printed circuit board (PCB) layout with direct board level design experience in RF or Microwave bands.</p> <p style="margin:0.15pt 0.0in 0.0in 14.95pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;font-family:'Times New Roman', serif"> </span>4 years of experience with basic Radar performance concepts.</p> <h1 style="margin:12.25pt 0.0in 0.0in 5.2pt;font-size:14.0pt;font-family:Verdana, sans-serif">Preferred Additional Skills:</h1> <p style="margin:12.2pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Master’s degree in Electrical Engineering or related field and/or equivalent experience desired.</p> <p style="margin:0.15pt 0.0in 0.0in 14.95pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;font-family:'Times New Roman', serif"> </span>Proficiency in python scripting.</p> <p style="margin:0.25pt 0.0in 1.0E-4pt 14.95pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;font-family:'Times New Roman', serif"> </span>Interest in leading a small technical team.</p> <p style="margin:0.2pt 0.0in 0.0in 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Excellent people skills to include collaborating in a multi-disciplinary, diverse, and dynamic team environment.</p> <p style="margin:0.15pt 57.55pt 1.0E-4pt 14.95pt;text-indent:0.0in;line-height:100%;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Excellent communication skills (written, verbal, &amp; presentation).</p> <p style="margin:0.15pt 57.55pt 1.0E-4pt 14.95pt;text-indent:0.0in;line-height:100%;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-family:'Times New Roman', serif"> </span>Active RF component design.</p> <p style="margin:0.15pt 0.0in 0.0in 14.95pt;text-indent:0.0in;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;font-family:'Times New Roman', serif"> </span>Radar Systems Design experience.</p> <p style="margin:0.2pt 28.75pt 1.0E-4pt 29.2pt;line-height:100%;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Familiarity with other design and analysis software such as MatLab, AWR, CDS, HFSS, or CST</p> <p style="line-height:100%;margin:0.15pt 0.0in 0.0in 29.2pt;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"><span><img src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAABmJLR0QA/wD/AP+gvaeTAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVQokZWSsQ3CQAxFv0N7RcIAVCfFNxH1bUCT7HC3BH0GIiCqWyBCcp9PQ6QUiARLv3vflu0PkiAJM3M55y6EcBORWUTmEMIt59yZmVs4kEQp5eS9fwLgN3nvn6WUE0nAzNwveG0yM3eo6/oyDMMZGzVN07FpmhdUddzqvuizn8wkZWsCAIgIqz3guqq2bR97YVW9VzHG615DjPH691n/f9w6GimlXlXHJRqqOqaU+nU03qGlnGhpd9e0AAAAAElFTkSuQmCC" width="6" height="6"></span><span style="font-size:10.0pt;line-height:100%;font-family:'Times New Roman', serif"> </span>Knowledge of practical RF system considerations such as path loss calculation, cascade noise figure and intercept point.</p> <p style="line-height:100%;margin:0.15pt 0.0in 0.0in 29.2pt;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"> </p> <p style="line-height:100%;margin:0.15pt 0.0in 0.0in 29.2pt;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"> </p> <p style="line-height:100%;margin:0.15pt 0.0in 0.0in 29.2pt;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"> </p> <p style="line-height:100%;margin:0.15pt 0.0in 0.0in 29.2pt;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"> </p> <p style="line-height:100%;margin:0.15pt 0.0in 0.0in 29.2pt;text-indent:-14.25pt;font-size:14.0pt;font-family:Verdana, sans-serif"> </p> <p style="margin:0.0in 0.0in 8.0pt;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif">#LI-KM1</p> <p><span style="font-family:verdana, geneva, sans-serif;font-size:14.0pt;color:black"> </span></p>