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Sr. Specialist, Electrical Engineer (FPGA) (Plano, TX, US, 75024-6612) @ L3Harris Technologies, Inc.

Plano, Texas, USOnsiteFull-time
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<p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Job Title: Sr Specialist, Electrical Engineer (FPGA)</span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Job Code: 40148</span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Job Location: Greenville, TX or Plano, TX (On-Site)</span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Job Schedule:</span></strong><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif"> 1st Shift 9/80</span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black"> </span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Job Description:</span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black"> </span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif">Electrical Engineering position with emphasis in System Verilog/VHDL development and verification for FPGA’s and Digital Signal Processing (DSP). The scope of the position requires a range of responsibilities spanning the following areas: requirements definition, conceptual trade studies, design and analysis, procurement, as well as integration and testing of FPGA designs. Electrical Engineers are responsible for participating in engineering analysis/evaluation efforts related to complex digital hardware systems, documenting design approaches, establishing design verification and validation procedures, and developing plans to manufacture and test sensor systems and major sub-assemblies.</span></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black"> </span></strong></p> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Essential Functions:</span></strong></p> <ul> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Requires knowledge of digital communication theory, experience in embedded processing, and experience in FPGA development utilizing VHDL and/or System Verilog.</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Candidate should also be knowledgeable about MATLAB and embedded software. </span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Candidate will work as part of a product development team in one or more of the following areas: algorithm modeling and simulation, coding using System Verilog and/or VHDL, Digital Signal Processing, FPGA development for Xilinx or Intel devices. Duties may include design, simulation, implementation and testing of hardware products; design/test documentation (specifications, design documents, test plan/procedures, etc.).</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Application areas include Digital Signal Processing, Audio/Data Distribution, and Communications for Airborne Intelligence, Surveillance and Reconnaissance Systems.</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Participating in Xilinx or Intel Field Programmable Gate Arrays (FPGAs) development in a team environment. </span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Performing engineering analysis and evaluation efforts of complex digital electronic systems in digital communications and/or digital signal processing </span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Documenting design approaches, following design verification and validation procedures, and developing plans to manufacture and test digital hardware units and subassemblies.</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Utilizing Xilinx or Intel FPGA development tools.</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Ability to obtain and maintain a DoD Clearance.</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Other duties as assigned by Supervisor.</span></li> </ul> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Qualifications:</span></strong></p> <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Bachelor’s degree with six (6) years of experience with FPGA Electrical Engineering.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Graduate degree with four (4) years of experience with FPGA Electrical Engineering.</span></li> <li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">In lieu of a degree, a minimum of eight (8) years of experience with FPGA Electrical Engineering.</span></li> <li style="line-height:normal;margin:0.0in 0.0in 8.0pt 0.0px;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Must be a U.S. Citizen.</span></li> </ul> <p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><strong><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Preferred Additional Skills:</span></strong></p> <ul> <li style="line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Proficiency in MS Office Suite.</span></li> <li style="line-height:107%;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">Strong communication, technical writing, and presentation skills</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience in DSP.</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience with Mentor Graphics Questa Sim/Modelsim/QuestaOne simulation tool.</span></li> <li style="line-height:normal;font-size:11.0pt;font-family:Aptos, sans-serif"><span style="font-size:14.0pt;font-family:Verdana, sans-serif;color:black">Experience generating cost &amp; schedule plans and estimates.</span></li> </ul> <p style="line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif;margin:0.0in 0.0in 0.0in 5.0px"><span style="font-size:8.0pt;line-height:107%;font-family:Verdana, sans-serif;color:black">#LI-AH1</span></p>

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