About this role
<p style="text-align:left"><span style="font-size:10.0pt"><span style="font-family:Arial, Helvetica, sans-serif">We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, <a href="http://www.teradyne.com/">Teradyne</a> companies deliver manufacturing automation across industries and applications around the world!</span></span></p> <p style="text-align:left"> </p> <p style="text-align:left"><span style="font-size:10.0pt"><span style="font-family:Arial, Helvetica, sans-serif">We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.</span></span></p><p> </p> <p> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif">Our Purpose</span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.<br><br>We cultivate a culture of inclusion for all employees that respect their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.<strong><br><br></strong></span></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif"><br>Opportunity Overview</span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Teradyne Nextest FPGA Team is looking for experienced verification engineer with passion to drive the product design quality to the highest level and contribute to company’s product success story. The verification engineer will be responsible for the planning, strategy, and execution of challenging FPGA verification projects and work under the technical supervision of a Verification Lead.</span></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">If you can proficiently do the following, then you are who we are looking for.</span></p> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Understand the design requirements from verification perspective</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Functional verification using System Verilog and UVM methodology</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Create testbench, verification components, and tests</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Create self-checking verification environment with data checkers and assertions</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Debug failures using waveforms and test log reports</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Drive verification completion with 100% functional coverage and code coverage</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">Interacting with FPGA design, software and hardware team for test strategies and debugging failures</span></li> </ul> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif"> </span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif">All About You<br></span></strong><span style="font-family:Arial, sans-serif">We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us on this mission, take a closer look at the minimum criteria for the position.</span></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif">Minimum Job Requirements:</span></strong></p> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">BS in Computer Science, Computer Engineering or Electrical Engineering. </span><span style="font-family:Arial, sans-serif">Or related field.</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">English proficiency.</span></li> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">8 years of experience with:</span></li> </ul> <ul style="list-style-type:square;margin-top:0.0in;margin-bottom:0.0in"> <li style="margin:0.0in 0.0in 0.0in 23.6px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">Digital Design functional verification</span></li> <li style="margin:0.0in 0.0in 0.0in 23.6px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">Industry standard protocols (e.g. PCIE, AXI)</span></li> <li style="margin:0.0in 0.0in 0.0in 23.6px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">EDA Tools (e.g. Cadence Xcelium, Simvision)</span></li> <li style="margin:0.0in 0.0in 0.0in 23.6px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">System Verilog.</span></li> <li style="margin:0.0in 0.0in 0.0in 23.6px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">UVM (Testbench components, development)</span></li> <li style="margin:0.0in 0.0in 0.0in 23.6px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">Verification IP integration</span></li> </ul> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif">Preferred Job Requirements:</span></strong></p> <ul style="margin-top:0.0in;margin-bottom:0.0in" type="disc"> <li style="margin-bottom:0.0in;margin-top:0.0in;margin-right:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><span style="font-family:Arial, sans-serif">MS degree in Computer Science, Computer Engineering or Electrical Engineering</span></li> </ul> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif"> </span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif"> The ideal candidate will demonstrate the following behavioral traits:</span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <ul style="margin-top:0.0in;margin-bottom:0.0in"> <li style="margin:0.0in 0.0in 0.0in 72.4px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">Excellent oral, written, and presentation skills.</span></li> <li style="margin:0.0in 0.0in 0.0in 72.4px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">Energetic team player who can work with a variety of people & disciplines.</span></li> <li style="margin:0.0in 0.0in 0.0in 72.4px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">Detailed oriented.</span></li> <li style="margin:0.0in 0.0in 0.0in 72.4px;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif;text-indent:0.4px"><span style="font-family:Arial, sans-serif">Results oriented.</span></li> </ul> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif">*This position is not eligible for visa sponsorship OR Relocation assistance</span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif"> </span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif">Benefits:</span></strong></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><strong><span style="font-family:Arial, sans-serif"> </span></strong><span style="font-family:Arial, sans-serif">Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, life and health insurance, paid vacation & holidays, tuition assistance programs, and more.</span></p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p> <p style="margin:0.0in;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"><em><span style="font-family:Arial, sans-serif"> </span></em><span style="font-family:Arial, sans-serif">#LI-PS1<br><br></span></p> <p style="margin:0.0in 0.0in 8.0pt;line-height:115%;font-size:12.0pt;font-family:Aptos, sans-serif"> </p>