About this role
<p style="margin:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:14.0pt;font-family:Arial, sans-serif;color:#c00000">Silicon Validation Engineer:</span></p> <p style="margin:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"> </p> <p style="margin:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><u><span style="font-size:11.0pt;font-family:Arial, sans-serif">Job description</span></u></p> <p style="margin:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Be part of the team that brings Winbond’s secure memory solutions to high level of functionality, reliability and performance. As a member in the post silicon and system validation group you will join the effort of validating, characterizing and debugging the silicon products and you will take part in developing the post silicon hardware infrastructure, software frameworks and automation tools. You will work closely with the architecture , design and application teams, completing a full validation cycle including tests definition, implementation and execution on pre and post silicon environments. During your daily work you will use advanced debug techniques and develop complex use-case scenarios to analyze silicon failures reported by users and customers.</span></p> <p style="margin:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"> </p> <p style="margin:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><u><span style="font-size:11.0pt;font-family:Arial, sans-serif">Key Qualifications</span></u></p> <ul style="margin-top:0.0cm;margin-bottom:0.0cm" type="disc"> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">BSc degree in Electrical or Computer Engineering</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Min of 5 years of experience in post silicon validation methodologies, tools and techniques</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Experience in Embedded SW development</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Experience in C and C++ and Python</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Experience in operating advanced lab equipment and measurement tools</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Team player with excellent communication skills</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Advantage: Experience in building test automation environments</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Advantage: VLSI or FPGA design//verification experience</span></li> <li style="margin-top:0.0cm;margin-right:0.0cm;margin-bottom:0.0cm;font-size:12.0pt;font-family:'Times New Roman', serif"><span style="font-size:11.0pt;font-family:Arial, sans-serif">Advantage: Experience in signal integrity validation</span></li> </ul>